A 5-MHz 11-bit delay-based self-oscillating ΣΔ modulator in 0.025 mm2

In this paper a self-oscillating Sigma Delta modulator is presented. By introducing this self-oscillation in the system, the loop filter operates at a speed significantly lower than dictated by the clock frequency. This allows for a simple and power efficient design of the opamps used in the loop filter. The self-oscillation is induced here by introducing a controlled delay in the feedback loop of the modulator. A second order CMOS prototype was constructed in a 0.18 um technology. A clock frequency of 850MHz generates a self-oscillation mode at 106.25 MHz. The modulator achieves a dynamic range (DR) of 66 dB for a signal bandwidth of 5 MHz. The power consumption is only 6mW and the chip area of the modulator core is 0.025mm^2

Simple quadrature oscillator for BIST

A simple quadrature oscillator for the built-in self-test (BIST) of integrated analogue filters is proposed. A new hardware-efficient approach for amplitude control is described, the main assets being: (i) the technique requires little hardware, which makes it very useful for BIST; (ii) the oscillation amplitude is well defined, and (iii) the distortion-level introduced by the amplitude control loop is under the control of the designer

Method for electric field and potential calculations in Hall plates

Electrostatic field problems occurring in Hall plates are difficult to solve, mainly because of a non-standard boundary condition defining an oblique angle of the electric field w.r.t. an isolating boundary. A new approach for solving Hall-related field problems is presented. Compared to prior approaches, the technique leads more easily to closed-form expressions for the electric field, and allows obtaining voltage-related Hall characteristics in numerically well conditioned forms

Improved DAC driving scheme for OFDM applications

Presented is a 'Redundant Signed Digit' driving scheme for binary weighted D/A conversion. This scheme retains the simplicity of conventional binary weighted D/A conversion, but has greatly improved robustness with regard to parasitic effects, especially when processing signals with a high crest factor. Such signals occur in communication systems that use, e.g. orthogonal frequency-division multiplexing (OFDM). In this case an improvement of 9 dB in Missing Tone Power Ratio performance was measured on a prototype 250 MSample/s circuit implemented in 0.18 mu m CMOS

Design of an integrated analog controller for a Class-D Audio Amplifier

An integrated analog controller for a self-oscillating class-D audio power amplifier is designed in a 0.35 μm CMOS technology for a 3.3 Volt power supply. It is intended to be used with an external output stage and passive filter, for medium power applications of upto a few 100 Watts. The controller was optimized with regard to its loop gain to suppress the distortion of the output stage. In typical commercially available output stages, the distortion is dominated by dead time effects and the THD can be as low as 20 dB. The controller uses self-oscillation to generate the carrier. To control the self-oscillation a second order phase shift network is embedded in the loop. To increase the loop gain a fifth-order loop filter is added. For a switching frequency of 400kHz the controller achieves a loop gain of 51 dB, nearly flat over the audio band. For reasons of flexibility, the order of the controller is made programmable, as well as the dead time and the delay in the loop. Full spice simulations of the controller combined with an external 120 Watt output stage indicate that a THD of upto 80 dB (better than 0.01%) can be obtained even under the worst case condition of a dead time of 50 ns

A rigorous approach to the robust design of continuous-time ΣΔ modulators

In this paper we present a framework for robust design of continuous-time Sigma Delta modulators. The approach allows to find a modulator which maintains its performance ( stability, guaranteed peak SNR, ...) over all the foreseen parasitic effects, provided it exists. For this purpose, we have introduced the S-figure as a criterion for the robustness of a continuous-time Sigma Delta modulator. This figure, inspired by the worst-case-distance methodology, indicates how close a design is to violating one of its performance requirements. Optimal robustness is obtained by optimizing this S-figure. The approach is illustrated through various design examples and is able to find modulators that are robust to excess loop delay, clock jitter and coefficient variations. As an application of the approach, we have quantified the effect of coefficient trimming. Even with poor trim resolution, good performance can be achieved provided beneficial initial system parameters are chosen. Another example illustrates the fact that also the out-of-band peaking behavior of the signal transfer function can be controlled with our design framework

Adressing static and dynamic errors in bandpass unit element multibit DAC's

This paper describes a general model for static as well as dynamic errors in multibit unit element DAC's. Apart from the static mismatch there are two other error terms arising from switching imperfections. Based on the model, some bandpass mismatch shaping techniques are presented. These address both the static mismatch as well as the switching imperfections. The techniques can significantly improve the in band noise

A selectable-bandwidth 3.5 mW, 0.03 mm(2) self-oscillating Sigma Delta modulator with 71 dB dynamic range at 5 MHz and 65 dB at 10 MHz bandwidth

In this paper we present a dual-mode third order continuous time Sigma Delta modulator that combines noise shaping and pulse-width-modulation (PWM). In our 0.18 micro-m CMOS prototype chip the clock frequency equals 1 GHz, but the PWM carrier is only around 125 MHz. By adjusting the loop filter, the ADC bandwidth can be set to 5 or 10 MHz. In the 5 MHz mode the peak SNDR equals 64 dB and the dynamic range 71 dB. In the 10 MHz mode the peak SNDR equals 58 dB and the DR 65 dB. This performance is achieved at an attractively low silicon area of 0.03 mm^2 and a power consumption of 3.5 mW

Analysis of VCO based noise shaping ADCs linearized by PWM modulation

Nonlinearity is one of the main problems associated with VCO based noise shaping ADCs. Their open loop architecture does not permit correction of the nonlinear voltage to frequency response of the VCO by feedback. Recently, linearization of a VCO ADC by Pulse Width Modulation (PWM) precoding has been proposed. Here, the input signal is encoded by a PWM modulator to drive the VCO with a 2-level signal, thus eliminating the nonlinearity of the VCO. This paper analyzes the remaining inherent distortion in such modulators which originates from subsampling the PWM sidebands

A closed-loop digitally controlled MEMS gyroscope with unconstrained Sigma-Delta force-feedback

In this paper, we describe the system architecture and prototype measurements of a MEMS gyroscope system with a resolution of 0.025 degrees/s/root Hz. The architecture makes extensive use of control loops, which are mostly in the digital domain. For the primary mode both the amplitude and the resonance frequency are tracked and controlled. The secondary mode readout is based on unconstrained Sigma Delta force-feedback, which does not require a compensation filter in the loop and thus allows more beneficial quantization noise shaping than prior designs of the same order. Due to the force-feedback, the gyroscope has ample dynamic range to correct the quadrature error in the digital domain. The largely digital setup also gives a lot of flexibility in characterization and testing, where system identification techniques have been used to characterize the sensors. This way, a parasitic direct electrical coupling between actuation and readout of the mass-spring systems was estimated and corrected in the digital domain. Special care is also given to the capacitive readout circuit, which operates in continuous time